Thread: Anandtech News

Intel just announced its latest SSD: the enterprise focused Intel SSD 710 series. The specs don't deviate very far from what we published a couple of months ago. The 710 uses Intel's own 3Gbps controller (same as the SSD 320) and firmware stack (newer than the SSD 320), but unlike the SSD 320 it uses a special version of Intel's 25nm MLC NAND. Intel calls it High Endurance Technology (HET) but in practice it's just MLC that sacrifices long term data retention for write cycles.

Standard MLC can retain your data for 12 months after you wear out the NAND, while HET MLC is specced to retain your data for only 3 months. In exchange you get 30x the number of write cycles as standard MLC. For enterprise workloads this tradeoff works quite well.

The SSD 710 will officially replace the X25-E, delivering nearly the same endurance with comparable performance, higher capacities and 40 - 50% cost savings. The 710 will be available in 100GB, 200GB and 300GB capacities.

Just like the SSD 320, the 710 employs a power safe write-cache, redundant NAND arrays to protect against NAND failures and AES-128 encryption.

A number of Intel's MLC SSDs have already been deployed in servers, the SSD 710 simply addresses some weaknesses with those drives while updating and formalizing the offering. Intel is expecting the lowest failure rate out of all of its SSDs with the 710.

Enterprise SSD Comparison
	Intel SSD 710	Intel X25-E	Intel SSD 320
Capacities	100 / 200 / 300GB	32 / 64GB	80 / 120 / 160 / 300 / 600GB
NAND	25nm HET MLC	50nm SLC	25nm MLC
Max Sequential Performance (Reads/Writes)	270 / 210 MBps	250 / 170 MBps	270 / 220 MBps
Max Random Performance (Reads/Writes)	38.5K / 2.7K IOPS	35K / 3.3K IOPS	39.5K / 600 IOPS
Endurance (Max Data Written)	500TB - 1.5PB	1 - 2PB	5 - 60TB
Encryption	AES-128	-	AES-128
Power Safe Write Cache	Y	N	Y
Temp Sensor	Y	N	N

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The HP Touchpad's troubled saga continues: the company's European arm is now offering partial refunds to anyone who brought the tablet at anything other than the bargain-basement fire sale price. The refund is for the difference between that clearance price and the price that the buyer originally paid, and the same courtesy is also being extended to buyers of the Pre3 smartphone, which never made it to the US.
Some retailers, like Best Buy in the US, have already been offering similar partial refunds to anyone who bought the Touchpad before HP pulled the plug, but others (including Amazon) have referred unhappy buyers to HP itself. Ths gesture should help to ameliorate any remaining ill will generated by the Touchpad and Pre3's quick discontinuation.
At this time, there's no word on whether HP is planning on extending this offer to the US or other territories.
Source: HP


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In another demonstration of silicon health AMD was showing working 28nm mobile GPU silicon running Dirt 3. It's too early to talk about performance or specifications, but AMD is still committed to a Q4 release for its 28nm GPU lineup.

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AMD's Bulldozer CPU is on the verge of being released. Sever markets will see the CPU soon, while desktop customers will have to wait until Q4 (which is only a month away at this point). No one likes to ship a delayed part, but if you do your job right the part that follows should arrive in a timely fashion. The follow-on to Bulldozer is called Piledriver and it will make its debut with AMD's Trinity APU in 2012.
Trinity is a higher end successor to Llano. It will integrate 2 - 4 Piledriver cores and feature some sort of a Radeon GPU on-die. Performance across the board will be higher than Llano. Piledriver should offer better performance per clock vs. Bulldozer, but Trinity won't be targeted at the same high-end market that AMD's FX series based on Bulldozer will address. Presumably we'll see a Piledriver based FX CPU at some point down the road. AMD indicated that Trinity was a few months away, implying an early 2012 launch.
To show the health of Trinity silicon, AMD showed it running Deus Ex in a suite a block away from IDF. The Trinity demo was done in a generic notebook chassis. We weren't allowed to benchmark the APU unfortunately. You can check out the demo in the video below:
If AMD can deliver Trinity in early 2012 and continue to execute beyond it, we may finally see the end of AMD's CPU woes. The company needs to put out a solid design and improve on it regularly. With Trinity following Bulldozer so closely, AMD may be doing just that.
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This afternoon (and yesterday) we had a chance to meet with a number of SoC vendors who have partnered with Microsoft for Windows 8. Each of them has their own individual reference tablet running Windows 8, and today we had a chance to survey the landscape and get photos of all the tablets. We started with ARM, then looked at x86 based tablets. Of course, the real goal with Windows 8 is to abstract as much of the difference between these two platforms away.
Unfortunately, all of the ARM vendors were required to keep their tablets under glass and out of the way of physical contact per Microsoft instruction. Microsoft isn't ready to show off the ARM version of Windows 8 for a variety of reasons at this point (at least without a Microsoft rep. present), but we still got a chance to at least take a look at what there is now. Microsoft is encouraging tablet makers to target either a 10.1" or 11.6" form factor with 1366x768 resolution.
Texas Instruments
First up is TI, whose development platform was demoed playing back the 1080p30 H.264 baseline video shown in the keynote fluidly in windows media player with a split-screen view. One tablet displayed the start menu, another displayed two split screen games. TI's development platform as shown right now is running on OMAP 4430, which again consists of two ARM Cortex A9s at 1.0 GHz and PowerVR SGX 540 graphics. Windows 8 won't launch on OMAP 4430, however, instead it'll launch on the mower powerful OMAP 4470 platform with PowerVR SGX544 graphics and a 2D display compositor. The reason is partly due to SGX544 having full DirectX 9.3 compliance, partly because it's an all around faster platform. I'm told that right now there's some DirectX emulation going on as well for all the SoCs that don't support DirectX 9.3.

I also recorded a short video showing the TI Windows 8 tablet in action.
Qualcomm
My next stop was Qualcomm, whose current development tablet runs on an MSM8660 SoC, which consists of two scorpion cores and Adreno 220 graphics. Qualcomm took the tablet out of the glass box for us and showed a quick demonstration of the start menu scrolling back and forth, and the IE10 mobile view working and scrolling around.

Unfortunately we weren't allowed to shoot video of the tablet while that demo was running, but we did grab some photos of the tablet without the glass box. Performance on the start menu looked to be above 30fps the whole time but not buttery smooth like the x86 tablets we've seen so far.

Just like TI, Qualcomm won't go to market with the SoC they're demonstrating Windows 8 working on today, instead they'll use the more powerful dual core Krait MSM8960 at first and quad core Krait APQ8064 later on. Dual core krait SoCs (eg 8960, 8270, 8260A) come with Adreno 225, quad core krait (APQ8064 and others) come with Adreno 320, both of which are DirectX 9.3.
NVIDIA
We've seen NVIDIA's Kal-El quad-core A9 based tablet a few times now, and found it out on the floor, also behind glass. Unlike the other vendors, NVIDIA hasn't said anything about going to market for Windows 8 with anything but Kal-El, and I don't see any reason why they should either.

The Kal-El development tablet was seated in a nice looking dock with what looks like one USB 3.0 port and a full size HDMI port.

AMD
Switching over to the x86 camp, we have AMD, who showed us two tablets running on Brazos - the Acer Iconia Tab W500 and MSI WindPad 110W, which use a C-50 and Z-01 APU, respectively. Displays on these are 1280x800 and support capacitive touch just like you'd expect for Windows 8.

Both the MSI WindPad and Iconia Tab felt snappy and responsive running the same Windows 8 Developer Preview build that we've used on the Samsung developer hardware. Subjectively, the WindPad's capacitive panel was more responsive and less prone to errant touch recognition than the Iconia, though both were more than useable with Windows 8. Intel

Last but not least is Intel's own development tablet, which is running an unnamed 32nm SoC. Intel was suspiciously silent about which particular SoC was inside this device, and you'll notice that it too is locked down in a plastic box, lumping it squarely in the next-gen SoC category for Microsoft.

It's possible this is Medfield, it's also possible this is some 2nd gen 32nm Atom SoC. Hopefully we'll find out more as Windows 8 starts getting closer to launch.


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When using the browser's Metro interface, Internet Explorer 10 will be completely plug-in free, says Microsoft's Dean Hachamovitch on the Building Windows 8 blog. The new browser will depend largely on HTML5 to serve ads, videos, and other traditionally plug-in-dependent content, which is in line with Apple's current strategy on the iPad. Also similarly, Hachamovitch cites "battery life as well as security, reliability, and privacy" as driving reasons to keep IE10 plug-in free.
This decision will most prominently affect Adobe's Flash, which is installed on the vast majority of desktop and laptop computers today and still drives much interactive Web content. In the face of increased competition from HTML5, Adobe has been buffing up both the Flash plug-in and its Flash development tools in recent months - Flash 11, currently available as a release candidate, brings 64-bit and 3D support to the plug-in, while the company is also working on Flash to HTML5 conversion tools. Adobe Edge, a new product currently in a preview state, will also be available to developers looking to replace Flash.
Microsoft's decision to go without plug-ins in its touch interface is an important one, but that doesn't mean they're completely going away - the non-Metro desktop version of IE 10 will still support plug-ins just as the browser currently does. This is consistent Windows 8's "no compromise" design philosophy - bring in the new without completely throwing out the old.
Source: Building Windows 8 Blog


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I met with LaCie this morning to talk about its upcoming Little Big Disk Thunderbolt storage solution. Unlike the Promise Pegasus R4/R6, the Little Big Disk only accommodates two 2.5" drives. LaCie will be offering both HDD and SSD options, although capacities will top out at 2TB for the HDD version and something much smaller for the SSD version.
The front of the chassis features a blue orb that lights up during disk accesses. It'll glow red if there's a problem with the setup. The orb also doubles as a power switch. There's no internal RAID controller, the drives rely on software RAID through OS X and by default will be configured as a RAID-0.
Although Thunderbolt can deliver up to 10W, the controller, cable and drives together end up exceeding that limit so LaCie will be bundling an external AC adapter with the Little Big Disk. Around back there are two Thunderbolt ports that allow you to daisy chain up to six of these Little Big Disks.
LaCie will be shipping the LBD this quarter. Pricing is TBD but we're eagerly awaiting our chance to review the chassis.
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Yesterday we published Ivy Bridge's transistor count as 1.48 billion. It turns out that was wrong as Intel's Mooly Eden accidentally read the B in billion as an 8 while on stage. The real number is 1.4 billion. When we published that story we compared it to Intel's Sandy Bridge, which at launch was said to be 995 million transistors. However at IDF Intel had been using another number: 1.16 billion transistors. It turns out both are right, but why is there a difference?
When designing a microprocessor you end up with a schematic of all of the circuits and transistors in the design. With the design schematic done layout is next on the list. However sometimes in the process of moving from the schematic to layout phase, transistor count baloons. The reason is simple. There are some circuits which may be represented by a single transistor at the schematic phase, but for more efficient layout use four transistors in tandem. For Sandy Bridge the 995M number is for the number of transistors in the schematic, while 1.16 billion is how many transistors are put down at the fab. Both are correct, but the 1.16B number is directly comparable to Ivy Bridge's 1.4B transistors.
That puts Ivy Bridge's transistor count at 20.7% higher than Sandy Bridge, which is more in line with what to expect from a tick.


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During the final keynote of IDF, Intel's Justin Rattner demonstrated a new stacked DRAM technology called the Hybrid Memory Cube (HMC). The need is clear: if CPU performance is to continue to scale, there can't be any bottlenecks preventing that scaling from happening. Memory bandwidth has always been a bottleneck we've been worried about as an industry. Ten years ago the worry was that parrallel DRAM interfaces wouldn't be able to cut it. Thankfully through tons of innovation we're able to put down 128-bit wide DRAM paths on mainstream motherboards and use some very high speed memories attached to it. What many thought couldn't be done became commonplace and affordable. The question is where do we go from there? DRAM frequencies won't scale forever and continually widening buses isn't exactly feasible.
Intel and Micron came up with an idea. Take a DRAM stack and mate it with a logic process (think CPU process, not DRAM fabs) layer for buffering and routing and you can deliver a very high bandwidth, low power DRAM. The buffer layer is actually key here because it helps solve the problem of routing pins to multiple DRAM die. By using a more advanced logic process it's likely that the problem of routing all of that data is made easier. It's this stacked DRAM + logic that's called the Hybrid Memory Cube.

The prototype these two companies developed is good for data rates of up to 1 terabit per second of bandwidth. Intel claims that the technology can deliver bandwidth at 7x the power efficiency of the most efficient DDR3 available today.
The big concern here is obviously manufacturing and by extension, cost. But as with all technologies in this industry, if there's a need, they'll find a way.


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Most modern day Intel CPUs run at or above 1V depending on clock speed. For years we had seen decreasing core voltages as Intel transitioned to lower power manufacturing processes, however in recent history it has remained almost flat. While actual transistor switching happens well below 1V, it's very difficult to accurately detect transistor state (off or on) at such low voltages. At what point are you measuring an actual switch vs. just noise? By mapping your high (or on) signal to higher voltages it's easier to tell when the transistor is actually on (e.g. 1V looks very different than 400mV, while 500mV doesn't).
Intel has done a lot of research into running CPUs near their threshold voltage (NTV), the actual voltage at which transistors begin conducting current. There's a lot of work that has to be done to make this happen but the end result is you get tremendous power savings. The chip Intel showed off today can run at less than 10mV (presumably when idle) and operate somewhere in the 400 - 500mV range when higher performance is needed.
In testing NTV Intel turned to its original Pentium architecture for the basis of the chip. The result was a chip that didn't require any heatsink to operate. This NVT Pentium won't be productized but the research will be used for future Intel many-core and ultra-mobile CPUs. Operating at lower voltages is important to both ends of the spectrum - whether you have dozens of cores or a handful of them in a phone, NTV operation would result in huge performance or battery life gains.


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